This tiny and cheap project should be very helpfully if your Atari has problem with so many modification inside and outside...
Genesis - PHI0 vs. PHI1 vs. PHI2 vs.... PHI2_BUF
6502 CPU using three clock signals for each operation:
- PHI0 - clock input - it's main clock source for CPU - for internally blocks using it to generate PHI1 and PHI2. This signal is generated by part of Antic (pin 34) from GTIA (pin 35) - 3.54MHz,
- PHI1 - clock output - generated from PHI0, used internally and for color phase generator,
- PHI2 - clock output - inverted PHI1 - main clock signal - most of Atari freaks thinking, PHI2 (Clock PHASE 2) signal is using to tick any IC connected to CPU bus. This signal is made directly by CPU and it's clock source only for Freddie (XE/XLF) and 74LS14 (XL)... Rest chips (and CART slot) are using: PHI2_BUF - buffered thru AND 74LS08 gate... yes - only one gate as a buffer!
So, in reality, the PHI2_BUF signal is used by so many ICs that its health is very poor - rising edges not as strong, phase floating, etc.
Known solutions
There are several known solutions available. Some of them are very easy and cheap. I would like to describe them briefly:
1. Just replace the 74LS08 with a 74F08 - this is the easiest method to upgrade the PHI2 - it is not a complete solution because all chips are still clocked by the original PHI2 directly from the CPU. Why does it work? Probably due to the short propagation time in the case of the F series (4-6ns for F vs. 12ns for LS).
This is the most commonly used solution and really useful.
2. A dedicated PCB called O2/Fixer with F08 type buffers, but implemented on separate gates - this solution stabilizes only PHI2_BUF for main chips and additional devices connected to PHI2_BUF through other F08 buffers. This solution is very similar to the above and works similarly.
3. Dedicated board under the processor with full buffered buses and signals - we can use the entire buffered signal, e.g. as in W65C02S for the Sally adapter: https://github.com/TheByteAttic/Sally-t ... Schematics %20W65C02S%20to%20Atari%20Sally%20Adapter%2020%20August%202020.pdf
Of course, this is just an example - you need to prepare a mezzanine. See "Clocks and /HALT generator block" on attached schematic.
4. The last solution I propose is to use special stabilization based on PLL + buffers (if necessary) - it is a kind of mezzanine, but installed under the processor. Only one wire (originally PHI2) needs to be cut and four wires (three without cables) should be soldered. The module is very thin and mounted between the processor pins and the sheet metal. This is fully buffered PHI2 with the same phase for each device. Only this solution guarantees that the load on the PHI2 processor pin is not so high as in the first and second cases.
- PhiXEL-PCB-3D Visualization
- PhiXEL-pcb.png (154.34 KiB) Viewed 3804 times
PhiXEL-visualization.mp4- PhiXEL 3D View Visualization
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First run...
I decided to install PhiXELv1 in my 800XL (without Freddy) because on board I've U1M, PokeyMax and other additional equipment... At First I use only Phase-Locked Loop chip only.
- PhiXEL with PLL chip only
- signal-2024-01-21-193812.jpeg (694.02 KiB) Viewed 3485 times
- PhiXEL with PLL and A800XL
- 800xl-phixel-pll.jpeg (756.22 KiB) Viewed 3485 times
- PHI2 buffered vs. original
- signal-2024-01-21-193759_008.jpeg (444.28 KiB) Viewed 3484 times